The invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body.
If, in applications of a field effect trench transistor, for example a DMOS power transistor as a high-side or low-side switch in motor vehicle ignition devices, a driver chip and the associated field effect power transistor are soldered separately on a circuit board, the leads may vary greatly depending on the application situation or customer requirements and, in principle, are exposed on the circuit board. This means that the signal exchange between the field effect trench transistor relating to signals from the temperature sensors and/or current sensors and the driver chip is subject to fluctuations in said leads and, moreover, there is the risk of individual or all components being destroyed by human ESD pulses coupled in via said leads. ESD pulses of this type may be coupled into the power transistor, for example, by the hand when touching such exposed regions or conductor tracks and destroy the gate oxide of said transistor.
In the case of an IGBT of the prior art, in order to protect the gate oxide from ESD pulses, planar diodes are provided between source metallization and gate metallization, as is illustrated for example in the accompanying FIG. 3. Here the planar diodes are realized by polysilicon diodes (n p n p n) on thick oxide above the silicon surface O and are contact-connected to a source metallization SM at one of their ends and to a gate metallization GM at their other end. In between, the surface of said polysilicon diodes is insulated by a dielectric DE. In order to obtain sufficiently low leakage currents and small drifts in this concept, the latter resorted to p+n polydiodes. By virtue of many individual diodes of this type being connected in series, it was possible to set reverse voltages as desired in steps of approximately 4 to 6 V depending on the number of diodes. If it were desired to integrate a concept of this type into a field effect trench transistor, this would result in disadvantages of a very large space requirement, for example in the chip edge region, and poor integrability into the process flow.
Many field effect trench transistors are usually subjected to an optimization of their on resistance relative to their gate charge or their gate capacitance in that a portion of the trenches (for example, every second trench) are formed as inactive trenches in which there are no gate electrodes arranged. This optimization is generally referred to as FoM (Figure of Merit) optimization.